Posts tagged d-states

ACPI power states list
posted on 2015-06-28 12:11:23

history

During the time of the APM standard (Advanced Power Management), power control was hardware-only: Call an ioctl on /dev/apm, the kernel then made a bios call, hardware took control and set things straight.

To allow OS-directed power management, ACPI (Advanced Configuration and Power Interface) was created.

overview

Now there exist state definitions in the ACPI standard for the

  • global system (G0 - G3)
  • system sleep states (S1 - S4 under G1)
  • device states (D0 - D3 hot / D3 cold)
  • processor states (C0 - C3)
  • performance states (P0 - Pn, in C0 or D0)

Generally the first state (ID 0) always defines a running/working mode without power savings or other power impediments.

g-states and s-states

G0 working
    S0 everything powered on like G0 - just monitor is turned off

G1 sleeping
    S1 power on suspend (POS) - CPU not doing instructions, CPU caches cleared, CPU and ram fully powered, some devices turned off
    S2 CPU off - CPU caches are flushed to RAM, CPU powerless
    S3 standby / suspend to ram (STR) - only RAM remains powered on
    S4 hibernate / suspend to disk - RAM saved to HDD/SSD, and all power is turned off.

G2 (S5) soft off - a little power to the motherboard, so the powerbutton or wake-on-lan etc. will work

G3 mechanical off - powered off via powerswitch of PSU (power supply unit), so the power cord can be removed safely

d-states

D0 fully on - full power

D1 intermediary state, definition depends on device

D2 intermediary state, definition depends on device

D3 off - unresponsive to the bus it is connected to
    D3 hot - has aux power, can assert power management request to transition to higher power states
    D3 cold - completely powered off

c-states

C0 operating state

C1 halt - no execution is done, but can return to C0 in an instant via signals

C2 stop clock - has to be awoken by hardware interrupts, external clocks run

C3 sleep - cache is not maintained coherently, takes longer to wake up, no external clocks run. See next table, too.

From here, a non-exhaustive list of processor power states:

MODE    NAME                   WHAT IT DOES                                                                CPUS

C0      Operating-State        CPU fully turned on                                                         All CPUs
C1      Halt                   Stops CPU main internal clocks via software;                                486DX4 and above
                               bus interface unit and APIC are kept running at full speed.
C1E     Enhanced-Halt          Stops CPU main internal clocks via software and reduces CPU voltage;        All socket LGA775 CPUs
                               bus interface unit and APIC are kept running at full speed.
C1E     —                      Stops all CPU internal clocks.                                              Turion 64, 65-nm Athlon X2 and Phenom CPUs
C2      Stop-Grant             Stops CPU main internal clocks via hardware;                                486DX4 and above
                               bus interface unit and APIC are kept running at full speed.
C2      Stop-Clock             Stops CPU internal and external clocks via hardware                         Only 486DX4, Pentium, Pentium MMX, K5, K6, K6-2, K6-III
C2E     Extended-Stop          Grant Stops CPU main internal clocks via hardware and reduces CPU voltage;  Core 2 Duo and above (Intel only)
                               bus interface unit and APIC are kept running at full speed.
C3      Sleep                  Stops all CPU internal clocks                                               Pentium II, Athlon and above, but not on Core 2 Duo E4000 and E6000
C3      Deep-Sleep             Stops all CPU internal and external clocks                                  Pentium II and above, but not on Core 2 Duo E4000 and E6000; Turion 64
C3      AltVID                 Stops all CPU internal clocks and reduces CPU voltage                       AMD Turion 64
C4      Deeper-Sleep           Reduces CPU voltage                                                         Pentium M and above, but not on Core 2 Duo E4000 and E6000 series; AMD Turion 64
C4E/C5  Enhanced-Deeper-Sleep  Reduces CPU voltage even more and turns off the memory cache                Core Solo, Core Duo and 45-nm mobile Core 2 Duo only
C6      Deep-Power-Down        Reduces the CPU internal voltage to any value, including 0V                 45-nm mobile Core 2 Duo only 

As can be seen here, intel defines up to 10 c-states, but this exceeds the ACPI specification.

The c-states can also be the source of time-sync errors in virtual machines. Since the hypervisor maybe cannot pass through the real-time clock, he may provide an emulated one, which in turn is related to the working cpu and its power states.

Energy consumption = no clock running = time halts

This can be the reason why your virtual machines are out of sync with the hypervisor clock every few days.

Disable the c-states in the BIOS, to make sure this will not happen, if your BIOS allows it.

p-states

Devices and CPU's running in D0 or C0 can have several p-states / performance states.

These are individually for the device / processor defined states in which the hardware can run:

P0 max power and frequency
P1 less than P0
P2 less than P1
...
Pn less than P(n-1)

This is what i.e. intel SpeedStep is about, throttling CPU power and frequency to achieve energy savings.

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